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Semiconductor Characteristic Simulation

Ever-shrinking form factors, more complex product integration and growing environmental compliance demands make semiconductor package performance and reliability improvement ever more challenging. The semiconductor package simulation solution reduces the need for fabricating test prototype by substituting actual test through test sample. SFA semiconductor’s provides best solution into the Mechanical, Thermal and Electrical Simulation under variety of manufacturing or operating condition.

Simulation License Simulation Service
Mechanical ANSYS Enterprise Package Warpage / Stress Room temp. after molding process High(Peak) temp. in reflow process
Package Reliability Solder fatigue Drop(Impact) / Bend test
Thermal 6 Sigma ET
Die Temperature
Package Thermal Resistance Theta-Ja, Theta-Jb, Theta-Jc
Package Characteristics Parameter Psi-Jt, Psi-Jb
Electrical ANSYS SI Wave
ANSYS Si option [Designer SI]
Parasitic Element extraction Characteristic Impedance
RLCG Parameter
Signal Integrity / PI TDR, Eye-Diagram S-Parameter

Mechanical Simulation

Deformation(Warpage) and stress in semiconductor package are a major concern for semiconductor package reliability. Mechanical simulation consider the impact of material property or manufacturing processes on the package. SFA Semiconductor’s offers the best solution for the deformation(warpage), stress and reliability prediction using ANSYS tools.

Unit Level Warpage Strip Level Warpage Deformation & Stress of Wire

Thermal Simulation

When the package is powered, heat is generated in the package due to thermal resistance. These thermal characteristics are very sensitive to maintaining the high reliability of the package. SFA Semiconductor’s offers solutions that meet JEDEC standard specifications and customer requirement to solve thermal issue.

Natural / Forced Convection (θ Ja/Jb/Jc) Thermal Characteristic in PCB Level

Electrical Simulation

Design guides reflecting electrical characteristics are provided at the PCB design stage, and after design is completed, parasitic components of each transmission track are extracted and provided to customers. It also analyzes the electrical performance of signal integrity in the frequency and time domain areas.

S-Parameter Eye-Diagram / TDR